Instruction Enhancement Programme (IEPs)
| # | TOPIC | SESSION | ORGANIZER | DURATION | MODE OF CONDUCTION | SESSION RECORDINGS |
|---|---|---|---|---|---|---|
| 1 | IEP on ASIC Digital Design Using 180nm PDK | Insights into RTL-to-GDSII using Cadence EDA Tools for Digital IC design with a focus on 180nm PDK | ChipIN Centre | 12-Feb-2024 to 16-Feb-2024 |
Hybrid |
ChipIN Centre IEP Session 1 ChipIN Centre IEP Session 2 ChipIN Centre IEP Session 3 ChipIN Centre IEP Session 4 ChipIN Centre IEP Session 5 |
| 2 | IEP on Memory and In-Memory Computing using SCL 180nm PDK on | Insights into CMOS IC Design Flow, Memory IP Design using SRAM and RRAM, Basic and Advanced Operations using In-Memory Computing and Fundamentals of Memory Compiler | IIT Indore | 18-Mar-2024 to 22-Mar-2024 |
Hybrid |
IIT Indore IEP Session 1 IIT Indore IEP Session 2 IIT Indore IEP Session 3 IIT Indore IEP Session 4 IIT Indore IEP Session 5 |
| 3 | Digital India RISC-V (DIR-V) architecture and applications | The sessions included a well-balanced mix of expert talks, hands-on training, and live demonstrations. Experts from the Shakti team of IIT Chennai, the VEGA team from C-DAC Thiruvananthapuram, and the NIELIT team handled the theory and practical sessions. | NIELIT Calicut | 9th-Dec-2024 to 13th-Dec-2024 |
Hybrid |
|
| 4 | IEP on ASIC Analog Design Using 180nm PDK (Hybrid) | Insights into Schematic-to-GDSII using Cadence and Siemens EDA Tools for Analog IC design with a focus on 180nm PDK | ChipIN Centre | 03-Feb-2025 to 07-Feb-2025 |
Hybrid |
ChipIN Centre IEP Day 1 ChipIN Centre IEP Day 5 |
| 5 | IEP on Standard Cell Design, Characterization, and Synthesis using SCL 180nm PDK | Insight into Standard Cell Circuit Design, Layout Design, Characterization, and Synthesis using the Cadence EDA tool using 180nm PDK | PES University, Bangalore | 22-Sept-2025 to 26-Sept-2025 |
Hybrid | |
| 6 | IEP on Digital Design, Logic Synthesis, and Implementation of Algorithms on FPGA | Designed to impart advanced training in FPGA-based digital system design with a focus on RTL modelling, custom accelerator development, signal processing, and Python integration | Aligarh Muslim University | 6-Nov-2025 to 10-Nov-2025 |
Hybrid |
AMU IEP Day 1 AMU IEP Day 2 AMU IEP Day 3 AMU IEP Day 4 AMU IEP Day 5 |
| 7 | IEP on RTL Design and Verification using Verilog | To learn & practice RTL Design and verification of complex digital circuits using Verilog HDL | Nielit Aurangabad | 24-Nov-2025 to 28-Nov-2025 |
Hybrid |
Nielit Aurangabad IEP Day 1 Nielit Aurangabad IEP Day 3 Nielit Aurangabad IEP Day 4 Nielit Aurangabad IEP Day 5 |
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