IEP on Memory and In-Memory Computing using SCL 180nm PDK on
Insights into CMOS IC Design Flow,
Memory IP Design using SRAM and RRAM,
Basic and Advanced Operations using In-Memory Computing and
Fundamentals of Memory Compiler
Digital India RISC-V (DIR-V) architecture and applications
The sessions included a well-balanced mix of expert talks, hands-on training, and live demonstrations. Experts from the Shakti team of IIT Chennai, the VEGA team from C-DAC Thiruvananthapuram, and the NIELIT team handled the theory and practical sessions.
