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Chips to Startup(C2S)

C2S Programme

In line with the objective and vision of NPE-2019, an umbrella programme "Chips to Startup(C2S)" not only aims at developing Specialized Manpower in VLSI/Embedded System Design domain but also addresses each entity of the Electronics value chain via Specialized Manpower training, Creation of reusable IPs repository, Design of application-oriented Systems/ASICs/FPGAs and deployment by academia/ R&D organization by way of leveraging the expertise available at Start-ups/MSMEs.

Participating Institutions

The programme would be implemented at about 100 academic institutions/R&D organizations across the Country. Besides them, Start-ups and MSMEs can also participate in the programme by submitting their proposals under Academia- Industry Collaborative Project, Grand Challenge/ /Hackathons/RFP for development of System/SoC/IP Core(s).

Identified Key Areas:

With a focus to develop frugal solutions around societal problem, it is envisioned that, under the programme, the project would be initiated in following key areas:

  • Energy & Environment
  • Healthcare
  • Agriculture
  • Disaster Management
  • Intelligent Transport System
  • Emerging Technology
  • Safety & Security etc.
  • Strategic sector etc.

Project Categorization

Under the Programme, based on the Institutions expertise, Technology Readiness Level (TRL) and design experience acquired during earlier SMDP Programmes, proposals would be invited in three different categories below from the Institutions, Startups and MSMEs for development. The details of category are given below:

A. Category-I: Design and Development of Systems/SoCs/ASICs/Reusable IP Core(s):

Category-I is open to all Academia, R&D Organizations, Startup and MSMEs having prior experience on development of Proof of Concept or Working Prototype. Under this category, following three types of projects are proposed to be supported:

i. Industry-Academia Collaborative Projects

Category-I - Industry-Academia Collaborative Projects are proposed to be initiated under C2S to strengthen the industry interactions with Academia and R&D organizations through collaborative research projects. It is proposed to initiate application-oriented R&D proposals jointly implemented by Academia/R&D organizations and Indian Startup(s)/MSMEs with part funding from Industry (preferably 10% of the overall budget as cash and not as kind).

The duration of such proposals would be up to 3 years with targeted Technology Readiness Level (TRL)-7 and above. The proposal would be supported for fabrication in MPW mode at any foundry based on the requirement of the project.

Note: Institutions applying under this category Projects may also submit individual Research Project proposal in Emerging areas. No separate funding would be provided for such projects. Such proposal would only be supported with common Infrastructure like EDA tool access and fabrication support in MPW mode.

ii. Grand Challenges/Hackathons

To foster the Indian Innovation and Research in the Country by developing affordable and sustainable solutions for Societal Problem catering to both global and domestic requirements, no of Grand Challenges/Hackathons would be organized for Academia/R&D organizations/Startups/MSMEs under the Programme.

The winning startups of Grand Challenge may also submit project proposal for product development as Industry-Academia collaborative project.

iii. RFP for design & development of IP Core(s)/System/SoC design(s)

In order to create an eco-system for globally competitive Indigenous Product and to boost domestic manufacturing in the Country, it is proposed to invite proposal from Academia/R&D organizations/Startups/MSMEs in RFP mode for development of IP Core(s)/System/SoC design(s).

B. Category-II: Development of Application Oriented Working Prototype of IPs/ASICs/SoCs

Under this Category, the application-oriented R&D proposals with duration up to 5 Years and targeted TRL level 7 would be invited from 40 Institutions in Consortium mode for development of ASIC/ SoC/System/IP Core(s). Such proposals should have the letter of interest/commitment from end user organization.

Any Institution other than 10 Resource Centre of SMDP-C2SD Programme can submit their proposal in Cluster of maximum 5 Institutions. Therefore, minimum 8 working prototypes of silicon proven IPs / ASICs / SoCs/Systems are expected to be delivered by 40 Institutions under this category. These proposals would be supported for fabrication at overseas foundry/SCL depending on the needs of the project.

Note: Institutions applying under this category Projects may also submit individual Research Project proposal in Emerging areas. No separate funding would be provided for such projects. Such proposal would only be supported with common Infrastructure like EDA tool access and fabrication support in MPW mode.

C. Category-III Proof of Concept oriented Research and Development of ASICs/FPGAs

To broaden the research base across the country in VLSI/Embedded design area by inclusion of new academic institution including SC/ST/Minority/Women institutions, it is proposed to invite call for Proposal from the 50 Government Institutions (mostly new) for development of Proof of Concept by taking ASIC and FPGA based designs. The proposals having letter of interest from end user organizations would be preferred for financial support by MeitY.

Under this Category, proposals for development of ASIC and FPGA based designs would be invited from Government Institutions including SMDP-C2SD category III Institution for duration of 5 year with targeted Technology Readiness Level up to 4. Such proposal would be supported for fabrication at SCL only.

It may be noted that these institutions may submit proposals in Category I and/or Category II also.

To continue the VLSI design culture at North Eastern region, it is proposed to include North East NITs/IIITs under the Programme in this category.

Keeping in view that most of the SMDP-C2SD Category III Institutions were earlier involved in development of FPGA based designs, it is envisaged that these institutions would preferably submit R&D proposals for ASIC based designs.

To encourage the students/researchers from SC/ST/Minority/Women community towards development in VLSI and Embedded System design area,Private SC/ST/Minority and Women University/Institution recognized by government would also be made part of the programme.

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