INNOVATE SOLUTIONS FOR # आत्मनिर्भर भारत

Students can submit proposals on other problem statements around VEGA and SHAKTI processor-based SoCs depending on feasibility.

Development of SoC for Plant Growth Monitor in Agriculture

This theme leverages IoT, sensors, and AI to enhance agricultural efficiency, productivity, and sustainability through precision farming. Focus areas include crop monitoring and real-time soil and environmental analysis. By integrating multiple sensors and machine learning as a custom IP core, the solution should support precision insights on an FPGA-based platform with VEGA/SHAKTI SoCs. This multi-node setup, supported by Zigbee communication, should enable a scalable and adaptable approach to real-time monitoring, optimized irrigation, and resource allocation in smart farming.

Proximity Warning System for Mobile Vehicle

The proximity warning system should enhance vehicle safety by using the IWR6843 radar sensor (or equivalent) to detect objects within a 40-meter range and classify them as vehicles, pedestrians, or obstacles. The VEGA/SHAKTI Core should execute a machine learning model to analyse detections, with data stored on an SD card for up to 24 hours. Real-time proximity information should be transmitted via CAN protocol. The system should be designed for outdoor reliability, resistance to vehicle vibrations, low power use, and high detection accuracy with <100 ms latency.

Strategic Sector Innovation in Object Detection

This theme addresses object detection for strategic applications like agriculture, diagnostics, surveillance, and defense. Using an FPGA-based platform with VEGA/SHAKTI SoCs, AI/ML accelerators, and an image sensor, this solution should perform real-time image processing, including RGB or YUV conversions and object detection using open-source Tensor libraries. The solution should involve training models in software and porting them onto hardware to accelerate processing, allowing efficient and fast detection across applications in strategic sectors.

Development of an SoC for Secure Communication

To address security challenges in data exchange, this solution should design an SoC with integrated data protection based on VEGA/SHAKTI cores. Features should include encryption, secure boot, and key management optimized for low power consumption and high performance. The cryptographic engine should support AES, RSA, and ECC algorithms, with a TRNG for secure key generation. This SoC is intended for applications such as IoT, financial systems, and healthcare, delivering robust data security and integrity for modern connected systems.

Two-Way Audio Communication

This solution should enable real-time two-way audio processing for IP cameras and similar devices, leveraging VEGA/SHAKTI RISC-V cores. It should ensure low-latency performance through efficient encoding, decoding, and audio streaming for applications in voice calls and video conferencing. Hardware support for codecs such as AAC, Opus, or G.711 should optimize audio quality and bandwidth. The design should also incorporate noise suppression, echo cancellation, and filtering algorithms for clarity, making it suitable for embedded systems where battery life is essential.

Low-Power Video Processing Accelerator with RISC-V Core

This accelerator IP should be designed for energy-efficient video processing in battery-operated devices, like drones or IoT cameras. It should offload tasks such as encoding and compression from the main processor, with capabilities for real-time video analytics like tracking, motion detection, and face recognition. The design should support H.264 or HEVC compression and scalability across resolutions from HD to 4K, enabling local video processing without cloud dependence and enhancing performance in surveillance, multimedia, and other mobile applications.

Secure Boot and Encrypted Storage with RISC-V Core

This solution should establish secure boot and encrypted storage for devices like IoT or automotive systems. A hardware-based secure boot should ensure only trusted firmware can execute, protecting against unauthorized access. Encrypted storage should secure firmware and video data using RISC-V-based encryption algorithms. This approach is intended to deliver robust, hardware-enforced security in IoT, automotive, and smart device applications, safeguarding sensitive information and preventing tampering.

Support offered under Incubation at Maker Village

1. The team could opt for physical or virtual incubation at Maker Village for a period of 1 year free of cost. The number of seats during this period would be restricted to 5 per team.
2. Teams would have access to electronics testing & measuring instruments, designing softwares, equipments for metal fabrications, Industrial grade 3D printers, PCB assembling etc. Teams would be charged at cost for usage of equipment which involves consumables and man hours and for testing & measuring instruments, teams could use it on returnable basis free of cost.
3. Teams would be provided with mentor support, connect with academia, industrial stake holders, domain experts etc. to fast track the product development as part of the incubation.
4. Teams could participate in various technical and business workshops conducted by experts in the ecosystem.
5. Teams would get opportunity to showcase their innovative products at various national expos.
6. Teams would also get first-hand information on various funding schemes from various central and state departments.
7. Teams would get an opportunity to interact with founders of successful startups and take insights from them on regular basis.

C-DAC's VEGA Processor

The DIR-V VEGA processor series marks a major step forward in India's journey toward self-reliance in processor design. Built using RISC-V ISA, VEGA includes a range of processors. The first VEGA-based chip has been successfully fabricated and integrated into development board, with more versions on the way. These processors are designed to support a variety of applications and contribute to strengthening India's domestic semiconductor ecosystem.

Details of the SoCs provided by VEGA team for the Grand Challenge can be found at: (https://vegaprocessors.in/dirv-grand-challenge.php)

IIT-Madras's Shakti Processor

The SHAKTI C64-A100 (Ganga) is a 64-bit C-class processor with a six-stage, in-order core supporting the RV64IMACSU extension. It includes two PMP regions, a two-cycle hardware multiplier, and a 32-cycle hardware divider. Equipped with 256 MB DDR memory and 4 KB ROM, it offers six PWM, two SPI, three UART, two I2C controllers, and 32 GPIOs. Key features include four timers, a platform-level interrupt controller (PLIC), an XADC from Xilinx, PinMux, Arduino-compatible pins, a CLINT for interrupt management, a JTAG debugger, and Ethernet Lite from Xilinx, making it versatile for varied application.

• Shakti SDK Manual [ Click here ]
• Shakti Soc Register Manual [ Click here ]

Artix7 100t FPGA boards ported with SoC based on VEGA/SHAKTI Microprocessor

The VEGA/SHAKTHI SoCs have been ported in soft-IP form into latest Artix7 FPGAs. The Artix7 FPGAs are part of the Xilinx 7 Series and offer a balance of performance, power efficiency, and cost-effectiveness. The Artix7 100t features 101,440 logic cells, 240 DSP slices, and 4.8 Mb of block RAM, making it suitable for a wide range of applications, including digital signal processing, embedded systems, and low-power designs. Its low power consumption and high performance make it ideal for portable and compact systems. Additionally, it is supported by Xilinx's Vivado Design Suite, which offers comprehensive tools for design, simulation, and debugging