Guidelines for Call for Proposal
GUIDELINES FOR SUBMISSION OF PROJECT PROPOSALS UNDER ALL
Academia/R&D Organizations/Startups/MSMEs while submitting
proposals for funding under Chips to Startup (C2S) Programme need
to fulfill the following requirements:
- Project Proposal should be submitted by Academia/R&D
Organization/Startup/MSME in the prescribed proforma of MeitY
available at C2S website.
- The proposal should be submitted by all
participating institutions in line with the project category
Here ] and as per definition of Technology Readiness Level (TRL)
[Click Here ].
- Remote access of EDA tool and fabrication support (in MPW
mode) would be provided to all participating institutions.
However, for Cat-I Projects (i.e. Industry-Academia
collaborative Projects), the fabrication cost will be part of the
budget outlay proposed by them under their project proposal and
for Category II & III projects, fabrication cost will be provided
separately (i.e. not budgeted under their project proposal)
- Project proposals should clearly indicate the
specification, novelty/USP of technology, Deliverables/ Outcomes,
Datasheet template for Soft/Hard IP Cores, targeted TRL,
technology node planned for fabrication, testing and prototyping
plans, scope and roadmap for commercialization and Transfer of
Technology etc. viz. field trialled deployable reusable IPs /
ASICs / SoCs / Systems or Working Prototypes or Proof of Concept
etc. with quarterly timelines.
- Proposals should clearly indicate the Resource
requirements in terms of EDA tools, manpower requirement etc. For
Category II & III Proposal, manpower salaries should be as per
extant DST norms.
- For Industry-Academia Collaborative Projects under
Category I, manpower salaries should be as per Institute norms
with which the collaboration is proposed or as per DST norms.
- Industry-Academia Collaborative project proposal having
part funding from End User Organization (preferably 10% (or more)
of overall budget) would be preferred by MeitY for support under
- The proposal submitted in consortium mode under Category
II, should have the letter of interest from end user organization.
- R&D project proposals having letter of interest from end
user organization would be preferred for support under Category
- An Institute can submit project proposals in any category
depending on the eligibility. In case of submission of multiple
proposals from institution, proposal would be selected for
financial support based on their merit in single category only.
The other proposals may be considered for providing remote access
of EDA tool and Fabrication support in MPW mode (Preferably at
- The Collaborative projects should clearly indicate Roles
and Responsibilities of nodal institute and each collaborating
institution (Startup/MSMEs/Academia/R&D Organization/End user),
their financial requirements/contribution along with quarterly
timelines for the project outcome.
- Nodal institute would be responsible for the Project
implementation, deliverable and fund disbursement to consortium
partners as per proposed Project milestones and timelines.
- The Participating Institutions/Startup/MSME should clearly
indicate name of Chief Investigator (CI) and Co-Investigator
(Co-CI) along with two faculty members. The project CI/Co-CI would
be responsible for coordination with PCI, MeitY, India Chip Centre
and Design Centre for timely completion of project activities.
- Institutions who are submitting the proposal in Category I
& II may also submit Research Project Proposal in Emerging areas.
The Proposals should be submitted in the same proposal format of
that Category (Only relevant fields to be filled), in which
Institution is applying. Such research proposals may be provided
with infrastructure support like access of EDA tools and
fabrication support in MPW mode (Preferably at SCL).
- It is mandatory for all academic Institutions
participating under the programme to provide commitment and plan
for 20-25 short term VLSI design projects for B. Tech/M.Tech/PhD
students as part of project proposal and to present the progress
report to PRSG.
- It is also mandatory for all academic Institutions to make
available basic infrastructure such as VLSI Lab, Work
Stations/Servers (in working condition), lab staff etc. during the
entire project duration. No separate hardware platforms like
workstations, servers, laptops, etc. would be provided under the
- Category I institutions will also participate in
developing Model Syllabus on VLSI and related areas under the
programme. It is mandatory for all the participating academic
institutions to adopt the model syllabus in their course
curriculum within two years of initiation of the programme.
- All the academic institutions should initiate M.Tech in
VLSI/embedded system, if not already done within 2-3 years of the
initiation of the programme.
- An MoU signed among all the collaborators including
Academia/R&D Organization/Startup/MSME/Industry/End users with
defined responsibilities needs to be submitted to PCI.
- The sharing of IP rights among collaborating agencies
would be as per the mutually agreed terms and conditions among the
collaborators and to be made and enclosed as part of the proposal.
- Milestone linked fund releases would be made to all
participating institutions by PCI.
- No separate funds would be provided for creation of new
facilities under the programme. However, the Institutions may
outsource the project activities like - PCB design/packaging etc.
within the approved outlay of the project, which cannot be
undertaken at the Institution. However, no R&D activity under the
project can be outsources by the institutions
- To the extent possible, efforts should be made to
fabricate the ASICs at SCL, Mohali.
- Patent should be filed for the "Research Component"
developed under the project before publishing it.
- It is mandatory for all participating Institutions to
implement the PFMS EAT 2 module at their institution within 60
days of project approval by MeitY. The GIA would not be released
to any institutions through PCI without PFMS implementation at the
institutions.After every release, each institute is mandated to
update the expenditure details at the PFMS EAT 2 portal on monthly
basis for the entire duration of project.
- It is mandatory for all academic Institutions to regularly
update the details of trained Manpower (Type-I, II, III, IV)
/Patent/Publication/ASIC/IP Core/System/SoC etc at the C2S website
as well as Institution website on monthly basis. Startup/MSMEs/R&D
organization to upload the details of manpower associated with the
project/Patent/Publication/ASIC/IP Core/System/SoC etc. at C2S
- The CI and Co-CI should have adequate experience of
working in VLSI design and related areas.
- Participating Institutions to restrict the proposal within
the budget outlay of that category in which proposal is being
- All positions of project staff will be co-terminus with
the project duration. MeitY would have no liability whatsoever for
sustaining such temporary staff after completion/termination of
- The CI/Co-CI and the project staff will not be transferred
to any other project for the entire duration of the programme.
- The participating Institutions would maintain financial
and other records as per norms and procedures laid down by MeitY
for the project and provide the details to PCI/MeitY whenever
- It is mandatory for all participating institutions to
submit Utilization Certificate as per GFR norms to PCI in the
financial year end and before request for next release.
- No commercial use will be made of the infrastructure
created, equipment/training material etc.
procured/supplied/developed under the project without the prior
approval of MeitY. Any liability for violation would have to be
borne by the participating institutions and may also result in
termination of the project.
- All the assets created/procured as part of the project
funds would be property of MeitY. At the end/termination of the
project, the MeitY would decide on the future use of such assets.
- All the items received under the project will be entered
in the appropriate Stock Registers. "Special Manpower Development
Programme for Chips to Startup, Ministry of Electronics &
Information Technology (Govt. of India)" would be suitably
displayed on the items. Loss and theft of any equipment/items
supplied under this project would be reported to appropriate
authority. Proper investigation by concerned authority would be
carried out and appropriate action would be taken. The same will
be reported to MeitY/PCI.
- The participating institutions would sign any
agreements(s) as may be required with the fabrication unit,
supplier(s) of hardware and software and Institution would be
solely responsible for any liability(ies) arising due to breach of
- The participating institutions should make efforts to
utilize the facilities set up under this project for carrying out
any other sponsored R&D projects sponsored by MeitY.
- The Head of the institution of the participating
institutions will make all efforts to ensure that the procedures
of the institution facilitate the smooth implementation of the
project and, if necessary, provide special dispensation for this
- In case faculty/students/researchers use the VLSI Lab
setup under this project for carrying out technical activities,
including publishing papers, which are not supported by MeitY,
they will acknowledge MeitY'ÂÂs name and will inform the
- The Project Proposal envisaging the use of Indigenous
Processor like VEGA Processor developed by CDAC [Details Here],
SHAKTI Processor developed by IIT Madras [Details Here] would be preferred for support.
The related design Infrastructure including the software tool
chain would be made available by Chip Centre, CDAC Bangalore to
- Kindly check the following before proposal
- All Supporting Documents (like AICTE Recognition
Certificate, NBA (National Board of Accreditation), NAAC
(National Assessment and Accreditation Council of UGC), Startup
Certificate, MSME Certificate etc.) based on the category of
proposal submission as applicable."
- Integrate all the supporting documents along with the
proposal as single PDF.
- All the documents and details are enclosed as per the
checklist in the project Proposal.
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