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India Chip Centre

Chip Centre was established at C-DAC, Bangalore for undertaking Siliconization of ASICs/Integrated Circuits designed by Special Development Programme-Chips to System design (SMDP-C2SD) Institutions. Chip Centre was the nodal centre for integrating the designs received from institutions and sending them to Semi-Conductor Laboratory (SCL), Chandigarh for fabrication in MPW mode. Chip Centre also facilitated the Institutions in packaging of bare dies received from SCL.

In order to provide exposure of complete VLSI design cycle to all Participating Institutions from specification to Fab tape out, it is upgraded to the capability and responsibility of existing Chip Centre and to establish a design Centre as part of Chip Centre for providing design support to the Institutions and Start-ups for development of ASIC and FPGA based designs.

Under current C2S programme, India Chip Centre will provide fabrication support at SCL and overseas foundries in MPW mode to Institutions/Start-ups/MSMEs. It also offer design services including maintaining IP Core Repository, Design flow establishment with a specific set of EDA tools and the Fab Process Design Kit (PDK) , Fab compliance validation of Designs, Packaging of Chips, Testing, Characterization in the Country in centralized manner.

Broad Responsibilities of India Chip Centre:

  1. India Chip Centre would be involved in following Major activities:
    • Design Verification and Integration of Fab Compliant MPW Tape outs
    • Fabrication Access at SCL and Overseas Foundries
    • Chip Packaging
    • Setting up a Repository of reusable IP Cores
    • Establishment of Design Flows with a specific set of EDA tools and the Foundry PDKs by tape out of designs in respective nodes and foundries.
    • Design and development of IPs / SoCs by Chip Centre for specific end applications in order to establish the IPs / ASICs / SoCs design flows with identified foundries and deriving a design flow process.
    • Facilitation for Patents/Copyrights and Trademarks for reusable IP Cores
    • Handholding of New Institutions/Start-ups for development of ASIC and FPGA based design
    • Creation of Design flow Guidelines / Best-Practices / Checklists / Report Templates
    • Coordinate/organize Workshop/Training Programme

  2. Digital ASIC/SoC Design Flow

  3. Design Compliance Flow for Fabrication

  4. Process flow- Reticle Planning to Packaged Chip

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